High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking dies vertically and interconnecting the dies using through-silicon (or through-substrate) vias (TSVs) have been introduced to provide larger memory capacity with a relatively small footprint. Benefits of the 3D memory devices include a plurality of dies stacked with a large number of vertical vias (TSVs) between the plurality of dies and the memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of dies, and a considerably small footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
The large number of vertical vias may transfer a clock signal, memory cell data and command sequences for controlling the dies simultaneously in a manner that the plurality of dies can be operated independently and/or simultaneously at high transfer rates. The 3D memory device may supply power to a plurality of dies including a large number of circuits that may operate simultaneously, which causes simultaneous power consumption throughout the device. However, there is voltage loss, such as voltage drop, across the plurality of dies mostly due to impedance of TSVs.
FIG. 1 is a schematic diagram of a portion of a semiconductor device 1 including a plurality of dies 4. The semiconductor device 1 may include a semiconductor package 2 that is mounted on a printed circuit board 8 via conductive balls 9. For example, the conductive balls 9 may be solder balls that function as sensing points of voltages used by a regulator (not shown) that adjusts power supply. The semiconductor package 2 may include a plurality of dies 4 mounted on a package substrate 3 via bumps 7. The plurality of dies 4 may include conductive vias 6 (e.g., through substrate electrodes) which couple the plurality of dies 4 by penetrating the plurality of dies 4 together with pillars 5 between the plurality of dies 4.
FIG. 2 is a simplified circuit diagram of a power supply circuit 10 in the semiconductor device 1. A sense ball 27 between the printed circuit board 8 and the package substrate 3 may be coupled to one of input nodes of an operational amplifier 21. Thus a voltage sensed at the sense ball 27 may be used as a reference voltage to adjust an output voltage of the operational amplifier 21. Thus, a voltage at the sense ball 27 may be adjusted using the output voltage of the operational amplifier 21. However, as a number of the plurality of dies 4 increases, the voltage drop becomes exacerbated due to the increased impedance 23 of the pillars 5 and conductive vias 6 in the plurality of dies 4, in addition to the impedance of a circuit component 22 in the package substrate 3. The voltage drop further becomes exacerbated due to on-die bussing of each die 4 and package bussing of the circuit board 8, each conductive ball 9 and each bumps 7. Such voltage drops are not reflected on the voltage at the sense ball 27 and uncompensated voltage drops are provided to the sense ball 27. The uncompensated voltage drop may cause unstable operations at portions of the large number of circuits.